Recently, planar miniaturization process is becoming difficult, and as a result, many stacked semiconductor memory devices in which memory transistors are three-dimensionally arranged have been proposed. Such a semiconductor memory device comprises a columnar semiconductor layer extending in a vertical direction with respect to a substrate and plural conductive layers surrounding a side surface of the columnar semiconductor layer through an insulating film and a charge accumulation layer. The columnar semiconductor layer functions as a body (channel) of plural memory transistors. The conductive layers each function as a control gate of the memory transistor.
However, in the stacked semiconductor memory device, after the conductive layer constituting the control gate and a select gate, and the insulating layer are alternately stacked, a memory hole is formed. Then, a MONOS film, for example, is formed in the hole, and therefore, because of its structure, only one charge accumulation layer is commonly provided with respect to the plural conductive layers. Accordingly, charge movement easily occurs between the memory transistors adjacent to each other, and there is a problem that data is not satisfactorily held. Thus, it is considered to adjust a threshold level of erasing and thereby improve data retention characteristics, in this case however, there is a problem that erase operation takes a long time.